The present invention relates to a semiconductor memory device and, more particularly, to a ROM whose memory cells are programmed by wirings corresponding to data to be stored.
Conventional custom ROMs of MOS ICs use MOS FETs of one type, e.g., n-channel MOS transistors, as memory cells. FIG. 1 shows a conventional custom ROM having a precharge circuit. The ROM in FIG. 1 has a 3-bit, 3-word memory capacity for the sake of simplicity. Word lines W0 to W2 are connected to the gates of corresponding word n-channel MOS transistors. One end of the current path of each n-channel MOS transistors is grounded and the other end thereof is selectively connected to corresponding bit line. For example, memory cell 10 is not connected to bit line B2 in order to store data "1", and memory cell 12 is connected to bit line B1 in order to store data "0".
The precharge circuit has MOS transistors 16A to 16C turned ON/OFF by clock signal .phi.. Bit lines B0 to B2 are respectively connected to a VDD terminal via the current paths of MOS transistors 16A to 16C.
During operation, MOS transistors 16A to 16C are rendered conductive for a predetermined period of time, every time word data is read out. Bit lines B0 to B2 are precharged to a VDD level, i.e., 5 V during this period of time. One of the word memories, e.g., a first word memory of memory cells 10, 12 and 14 is selected after the predetermined period of time. In this case, bit lines B0 and B1 are discharged through memory cells 12 and 14, while bit line B2 is kept precharged. Word data "100" is thus read out from memory cells 10, 12, and 14 onto bit lines B2 to B0.
However, the above arrangement is not suitable for manufacturing a ROM utilizing a CMOS master slice chip (or a gate array chip). A CMOS master slice chip uniformly has p- and n-channel MOS transistors. For this reason, when only n-channel MOS transistors are used as the memory cells, many p-channel MOS transistors thereof must be left unused.
The ROM in FIG. 1 requires clock signal .phi. for controlling turning ON/OFF of MOS transistors 16A to 16C. Signal .phi. must be synchronized with a timing for selecting each word memory, which complicates the structure of a clock generator (not shown).
FIG. 2 shows a conventional custom ROM having a pull-up circuit. The ROM in FIG. 2 has the same structure as that of FIG. 1, except that the precharge circuit is replaced by a pull-up circuit. The pull-up circuit consists of resistors 18A to 18C each having one end connected to a VDD terminal and the other end connected to a corresponding one of bit lines B0 to B2, respectively.
The above arrangement is also not suitable for manufacturing a ROM utilizing a CMOS master slice chip, for the same reason as for the ROM of FIG. 1. In addition, the current flowing in resistors 18A to 18C is another drawback in this type of ROM. Resistor 18C and the MOS resistors of memory cells 20 and 22 constitute a ratio circuit. Currents of different values flow constantly in resistor 18C in accordance with stored data. This is undesirable in the interest of decreasing the power consumption of the ROM.